Prior to joining CMU in 2015, I recieved my B.S. degree in 2012 and M.S. degree in 2014 both in Electrical Engineering from Beihang University, China.
I’m an FPGA enthusiast. I have built various FPGA-based systems in past years. In recent years, my research interests lie in the intersection of FPGA and networking.
I will “rejoin” Microsoft Catapult Team in 2021 summer!
- We Need Kernel Interposition over the Network Dataplane
Hugo Sadok, Zhipeng Zhao, Valerie Choung, Nirav Atre, Daniel S. Berger, James C. Hoe, Aurojit Panda, Justine Sherry
- Beyond Peak Performance: Comparing The Real Performance of AI-Optimized FPGAs and GPUs
[paper | video]
Andrew Boutros, Eriko Nurvitadhi, Rui Ma, Sergey Gribok, Zhipeng Zhao, James C. Hoe, Vaughn Betz, Martin Langhammer
IEEE FPT, 2020
- Achieving 100Gbps Intrusion Prevention on a Single Server
[paper | video | code | the morning paper]
Zhipeng Zhao, Hugo Sadok, Nirav Atre, James C. Hoe, Vyas Sekar, Justine Sherry
USENIX OSDI, 2020
- Using Vivado-HLS for Structural Design: a NoC Case Study(Poster)
[poster | tech report | code]
Zhipeng Zhao, James C. Hoe
ACM FPGA, 2017
Load Balancer for Networked FPGAs (2017 Summer, Microsoft)
Intern on the Catapult Team, working on balancing the Bing Search load across networked FPGAs to reduce the tail latency, mentored by Adrian Caulfield and Michael Papamichael. Designed and implemented a load balancer on FPGA that is fair, adaptive (i.e. quickly rebalance the load when worker node failure happens), fast (i.e. introduce little latency overhead in single-digit microsecond latency target) and small (i.e. consuming minimal FPGA resources).
[Fun Fact]: My interests in networking started from a random chat with Qiao Zhang, who was a PhD student from University of Washington, during a boat cruise intern event.
Flash-Array Data Recorder (2014, Beihang University)
The portable Flash-Array data recorder is used to record the sampled signal waveform and upload the data to computer for offline analysis. Developed the core control logic in FPGA that collects sampled waveform from Analog-to-Digital Converter (ADC), controls Flash-Array, and communicates with computer through Gigabit Ethernet.
[Fun Fact]: I burned out a $5000 FPGA (has large number of IO pins) in this project.
Multi-FPGA/DSP Interconnect (2012-2013, Beihang University)
Designed and implemented the high-speed interconnections (e.g. PCIe, SRIO) between FPGAs and DSPs in three different real-time signal processing systems.
[Fun Fact]: I soldered tons of 0402 components for our custom boards. It was really enjoyable (I can do this all day). However, debugging custom boards was another story…
Software-Defined Radio Transceiver (2012-2013, Beihang University)
The software-defined radio transceiver can apply various signal processing algorithms selected by controller (a separate device). Independently completed the prototype, including board schematic design, PCB layout, developing FPGA logic (controlling ADC, DAC and serial port communication), and system verification with engineers from industry.
[Fun Fact]: My first PCB was a failure due to the short circuit in the design.
Arbitrary Wave Generator (2012, Beihang University)
The arbitrary wave generator serves as the test input for many signal processing systems. Implemented the waveform generation datapath in FPGA, accepting waveform data from embeded computer PC104, storing the data in off-chip SRAM, and then replaying the waveform through DAC repeatedly.
[Fun Fact]: This was the first time I touched an FPGA board. The moment I lit the LED using FPGA also lit up my passion for FPGA. That was how everything began.